1. Field of the Invention
The present invention relates to a PLL or DLL circuit, especially to a circuit for controlling a duty ratio of a signal.
2. Description of the Background Art
When an input clock signal having a high period/low period ratio or duty ratio of one to one is fed to a circuit, the duty ratio may deviate from 1:1 inside the circuit, for example, due to the level of the input clock signal or the characteristics of an input buffer. Further, in some cases, the duty ratio of the input clock signal which is generated in the PLL or DLL circuit may not be 1:1 due to imperfect oscillation characteristics of a voltage controlled oscillator or a delay stage.
With the duty ratio of other than 1:1, a problem will arise, for example, when both rising and falling edges of the input clock signal are used as timing signals for the operation of logic elements in the circuit. More specifically, the deviation of the duty ratio from 1:1 increases the risk that a time when an element starts its operation at the rising edge may coincide with a time when the element starts its operation at the falling edge. This causes a shortage of timing margins.
FIG. 13 shows circuitry for correcting the duty ratio of the clock signal to 1:1, which resolves the above problem. This circuitry is designed to incorporate a duty-ratio correction circuit DRC3 into a well-known PLL circuit PLL1, disclosed for example in R. Bhagwan and A. Rogers, "A 1 GHz Dual-Loop Microprocessor PLL with Instant Frequency Shifting", ISSCC Digest of Technical Papers, pp. 336-337, February, 1997.
First, we will describe the operation of the PLL circuit PLL1. An input clock signal S1 and a feedback clock signal S2 are frequency-divided by frequency dividers CD1 and CD2, respectively, and fed to a phase-frequency detector 6. The phase-frequency detector 6 detects a coincidence or phase difference between those signals and outputs a signal S3 for indicating the intensity of voltage which is responsive to the detection result, to a charge pump 7. Converting the signal S3 into a current signal S4, the charge pump 7 acts as a charge supply source for a loop filter 8. The loop filter 8 includes a capacitor C3 whose one end is connected to a power source VDD (showing the potential at that end also as "VDD"), so the potential of the other end is smoothed to be a signal S5 to a voltage controlled oscillator 5. The signal S5 varies an oscillation period and a phase of a signal S6 output from the voltage controlled oscillator 5.
In a standard PLL circuit, the signal S6 directly becomes the feedback clock signal S2. In the circuitry in FIG. 13, on the other hand, the signal S6 is fed to the duty-ratio correction circuit DRC3. Then, a signal S7 outputted from the duty-ratio correction circuit DRC3 becomes the feedback clock signal S2 through a buffer B1.
Next, we will describe the duty-ratio correction circuit DRC3. The duty-ratio correction circuit DRC3 consists of a level shifting circuit LS1, a duty-ratio detecting circuit 2, and a duty-ratio correction filter 3.
The level shifting circuit LS1 varies a threshold value of the signal S6 for determining the transition timing of the signal S7. By using the level shifting circuit LS1, the threshold value can be shifted from an intermediate value between high and low which is usually used as a threshold voltage. Thus, the duty ratio of the signal S6 becomes variable.
FIG. 14 is a timing chart of the operation of the level shifting circuit LS1. It shows waveforms S7a, S70, and S7b of the signal S7 when a threshold value Vref of the signal S6 is Vrefa, Vref0, and Vrefb, respectively, where Vrefa&lt;Vref0&lt;Vrefb.
As shown in FIG. 14, a rising edge of the signal S7 becomes earlier and a falling edge thereof becomes later with the decrease in the threshold value Vref. That is, a high period of the signal S7 increases. On the other hand, a low period of the signal S7 increases as the threshold value Vref increases.
The duty-ratio detecting circuit 2 is a charge pump for converting the signal S7 into a current signal S8, and the duty-ratio correction filter 3 is a filter including a capacitor C2 whose one end is grounded (showing the potential of that end as GND). The signal S7 is fed to the duty-ratio detecting circuit 2 to be converted into the signal S8. The signal S8 is then converted into a control signal S9 which is a smooth voltage signal, by the capacitor C2 in the duty-ratio correction filter 3. The control signal S9 is fed back to the level shifting circuit LS1, by which the amount of level shift is controlled to correct the duty ratio to 1:1.
As described so far, this circuitry comprises two feedback mechanisms, including a loop in the PLL circuit PLL1 for controlling the phase and the period and a loop in the duty-ratio correction circuit DRC3 for controlling the duty ratio to be 1:1.
In the circuitry, however, either of the two feedback mechanisms for the feedback clock signal S2 is likely to interfere with the other. Thus, it may take more time to stabilize the circuitry as compared with a case where the PLL circuit PLL1 and the duty-ratio correction circuit DRC3 are separated to operate independently.